View STEL-1176MC_3515326.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

r

-" !)' .% & / ')0 &/%)
stel-1176 2 features n high clock frequency C 80 mhz maximum over commer- cial operating conditions n high frequency resolution with decimal frequency steps C precisely 0.1 hz @ 80 mhz n very high speed frequency hopping or modulation C max. update speed 250 nanosecs. n precision phase modulation C 3 bits for 8ary psk n high resolution output C 12 bits n high spectral purity C all spurs < C72 dbc n parallel or byte-wide control inputs n low power dissipation applications n precision synthesizers n instrumentation n carrier generation block diagram phld frld address select logic addr csel wrs tb -phase buffe r registers data 35 clock 35 -phase register 8 3 / 4 decade phase accumu- lator 35 35 phase alu 15 3 sine lut 12 out ldc lk re fc lk 3 cin reset to all registers 15 phase 2/8/16 clksel phase buffe r register functional description the stel-1176 numerically controlled oscillator (nco) uses digital techniques to provide a cost- effective solution for the generation of low noise, high resolution signals. the nco devices combines low power 1.5 m cmos technology with a unique architectural design resulting in a power efficient, high-speed sinusoidal waveform generator. this performance is enhanced by its rapid frequency switching capability and parallel control interface. the stel-1176 features high frequency resolution in a decimal format, with extremely low spurious signal levels and a high maximum operating frequency. the decimal frequency resolution allows frequencies to be generated in exact multiples of 0.1 hz from a standard reference frequency, such as 10 mhz, and the divided clock output at 5 or 10 mhz is provided to facilitate this. the frequency control data format is 1-2-4-8 bcd, and the unique architecture allow the data to be loaded either as a 35-bit parallel word, for maximum speed, or as five bytes, for easy microprocessor interfacing. the stel-1176 also features 3-bit phase modulation, allowing the output to be modulated with bpsk, qpsk or 8ary psk data. the output frequency can be calculated from the following equation: f c x d -phase f o = 8 x 10 8 where: f o is the frequency of the output signal and: f c is the clock frequency.
3 stel-1176 package: 84 pin plcc thermal coefficient, q ja = 30 /w 0.200" max. 1.190" 0.005" 33333334444 4444445555 34567890123 4567890123 1 1 8888877777 10987654321432 1098765 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 0.145" max. 0.017" 0.004" (2) 0.004" (2) 0.018" 0.035" n omina l 1.150" 0.012" 1 1 8 888 87 777 7 10 98 765 432 14 321 09 876 5 74 73 333 33 334 44 44 444 44 55 55 345 67 890 12 34 567 89 01 23 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1.154" 0.004" 0.05" nominal (1 ) 0.05" 0.005" (1) top view top view package: 84 pin cldcc thermal coefficient, q ja = 34 /w note: tolerances on pin spacing are not cumulative. pin configuration note: i.c. denotes internal connection. these pins must be left unconnected. do not use for vias. 18 data 6 19 v ss 20 v dd 21 v ss 22 v ss 23 clock 24 v ss 25 data 7 26 data 8 27 data 9 28 data 10 29 data 11 30 data 12 31 data 13 32 data 14 33 v dd 34 data 15 35 data 16 36 data 17 37 data 18 38 data 19 39 data 20 40 data 21 41 data 22 42 data 23 43 v ss 44 v ss 45 data 24 46 data 25 47 data 26 48 data 27 49 data 28 50 data 29 51 data 30 52 data 31 53 data 32 54 v dd 55 data 33 56 data 34 57 i.c. 58 v ss 59 out 0 60 out 1 61 out 2 62 out 3 63 v ss 64 v ss 65 out 4 66 out 5 67 out 6 68 out 7 69 v ss 70 out 8 71 out 9 72 out 10 73 out 11 74 v dd 75 v dd 76 ldclk 77 v ss 78 refclk 79 v ss 80 phld 81 phase 0 82 phase 1 83 phase 2 84 v ss pin connections 1v ss 2 reset 3 cin 4 clksel 5 addr 0 6 addr 1 7 addr 2 8 wrstb 9 csel 10 frld 11 data 0 12 v dd 13 data 1 14 data 2 15 data 3 16 data 4 17 data 5
stel-1176 4 circuit description the stel-1176 features a dual mode input port which can be set up to allow either byte-wide or parallel loading of the bcd frequency control data. the input is double buffered, and the new frequency data is loaded on the first or second rising edge of the clock (whichever occurs while ldclk is low) after the falling edge of the frld signal. a 3-bit phase modulator is also incorporated, and the phase modulation (pm) data is loaded separately on its own bus. a bcd technique is used to create an nco with a frequency resolution which has a decimal relationship to the clock frequency. this is achieved by providing nearly nine decades of accumulation with a range of 0 to 799,999,999. any value within this range may be loaded into the d -phase register as a frequency control word. within this range a total of 80 x 10 7 values exist, so that when the nco is operating at a clock frequency of 80 mhz, the output frequency resolution will be precisely 0.1 hz. the 80 mhz clock is divided by eight or sixteen internally, and the divided clock is provided as an output at 10 mhz or 5 mhz. this output can be used to phase lock the 80 mhz clock generator to a reference standard. the fifteen msbs of the accumulator are used to address a unique lookup table. the lookup table generates a sinewave output with twelve bits of amplitude resolution. this results in a typical overall spurious performance of C72 dbc, or better. the nco generates a sampled sine wave where the sampling function is the clock. the practical upper limit of the nco output frequency is about 40% of the clock frequency due to spurious components that are created by sampling. those components are at frequencies greater than half the clock frequency, and become more difficult to remove by filtering. the phase noise of the nco output signal may be determined from the phase noise of the clock signal input and the ratio of the output frequency to the clock frequency. this ratio squared times the phase noise power of the clock specified in a given bandwidth is the phase noise power that may be expected in that same bandwidth relative to the output frequency. the nco achieves its high operating frequency by making extensive use of pipelining in its architecture. the pipeline delays within the nco represent 37 clock cycles. the pipeline delay associated with the phase modulator is only 17 clock cycles, since the phase modulating function is at the output of the accumulator. the phase modulation may also be changed as rapidly as every clock cycle. note that when a phase or frequency change occurs at the output the change is instantaneous, i.e., it occurs in one clock cycle, with complete phase coherence. function block description address select logic block this block controls the writing of data into the device via the data 34-0 inputs and the phase 2-0 inputs. the data is written into the device on the rising edge of the wrstb input, and the mode (35-bit parallel or byte-wide) and register into which the data is written is selected by the addr 2-0 inputs. the csel input can be used to selectively enable the writing of data from the bus. d -phase buffer register block the d -phase buffer register block is used to temporarily store the d -phase data written into the device. this allows the data to be written asynchronously as a 35-bit word or as five bytes per 35-bit d -phase word. the data is transferred from these registers into the d -phase register after a falling edge on the frld input. phase buffer register block the phase buffer register block is used to temporarily store the pm data written into the device. the data is transferred from this register into the phase alu after a falling edge on the phld input. d -phase register block this block controls the updating of the d -phase data used in the accumulator. the frequency data from the d -phase buffer register block is loaded into this block after a falling edge on the frld input. phase accumulator block this block forms the core of the nco function. it is a high-speed, pipelined, 35-bit parallel bcd accumulator, generating a new sum in every clock cycle. unlike other ncos, the arithmetic used in the stel-1176 is bcd, making the resolution of the device decimal. the 35 bits make up 8 3 /4 decades, so that the full-scale count of the accumulator is 799,999,999. this makes the frequency resolution 1 part in 800,000,000, or 0.1 hz in 80 mhz. a carry input (the cin input) allows the resolution of the accumulator
5 stel-1176 to be expanded by means of an auxiliary nco or phase accumulator. the overflow signal is discarded, since the required output is the modulo(8x10 8 ) sum only. this represents the modulo(2 p ) phase angle. phase alu block the phase alu performs the addition of the pm data to the phase accumulator output. the pm data word is 3 bits wide, and this is added to the 3 most significant bits from the phase accumulator to form the 15-bit modulated phase used to address the lookup table. sine lookup table block this block is the sine memory. the 15 bits from the phase accumulator and alu are used to address this memory to generate the 12-bit out 11-0 outputs. clock divider block the incoming system clock is divided by two and the half speed clock ( ldclk ) is used in the d -phase register block. the ldclk is further divided by four or eight, depending on the state of the clksel input, to provide the refclk output. this output may be used in a pll circuit to lock the 80 mhz clock generator to a 10 mhz or 5 mhz reference standard. input signals reset the reset input is asynchronous and active low, and clears all the registers in the device. when reset goes low, all registers are cleared within 13 nsecs, and normal operation will resume after this signal returns high. the data on the out 11-0 bus will then be invalid for 10 clock cycles, and thereafter will remain at the value corresponding to zero phase (801h) until new frequency or phase data is loaded with the frld or phld inputs after the reset returns high. clock all synchronous functions performed within the nco are referenced to the rising edge of the clock input. the clock signal should nominally be a square wave at a maximum frequency of 80 mhz. a non- repetitive clock waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 5 nanoseconds. csel the c hip sel ect input is used to control the writing of data into the chip. it is active low. when this input is high all data writing via the data 7-0 bus is inhibited. data 34 through data 0 the 35-bit data 34-0 bus is used to program the 35-bit d -phase register. data 0 is the least significant bit of the bus. the data programmed into the d -phase register in this way determines the output frequency of the nco. the data will be loaded as a parallel 35- bit word or as five bytes, depending on the state of the address bus, as shown in the address table. each nibble (4 bits) of data starting at data 3-0 represents one decade of frequency data in 1-2-4-8 bcd format. when the byte-wide mode is selected (addresses 000 to 100), the 35 data lines must be connected externally to form an 8-bit data bus as follows: connect data 34-32 to data 2-0 , data 31-24 to data 23-16 to data 15-8 to data 7-0 . phase 2 through phase 0 the 3-bit phase 2-0 bus is used to program the 3-bit phase register. phase 0 is the least significant bit of the bus. phase 2 corresponds to an incremental phase shift of 180 , phase 1 corresponds to an incremental phase shift of 90 , and phase 0 corresponds to an incremental phase shift of 45 . addr 2 through addr 0 the three address lines addr 2-0 control the use of the data 34-0 bus for writing frequency data to the d -phase buffer register and the phase 2-0 bus for writing phase data to the phase buffer register, as shown in the table: addr 2 addr 1 addr 0 register field 000 d -phase bits 7-0 (lsb) 1 001 d -phase bits 15-8 1 010 d -phase bits 23-16 1 011 d -phase bits 30-24 1 100 d -phase bits 34-32 1 1 0 1 phase bits 2-0 110 d -phase bits 34-0 2 111 d -phase + phase bits 3 it is not necessary to reload unchanged bytes, and the byte loading sequence may be random. notes: 1. byte-wide frequency loading mode. 2. parallel frequency loading mode. 3. loads the frequency data in the parallel mode and the phase data simultaneously.
stel-1176 6 output signals out 11-0 the signal appearing on the out 11-0 output bus is derived from the 15 most significant bits of the phase accumulator via the phase alu. the 12-bit sine function is presented in offset binary format. the value of the output for a given phase value follows the relationship when the phase modulation is zero: out 11-0 =2047 x sin (360 x (phase+0.5)/8000) +2048 the result is accurate to within 1 lsb. when the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 2049 (801 h ). refclk the r eference cl o ck output signal is the clock input divided by either eight or sixteen, depending on the state of the clksel input. when the input clock frequency is set to 80 mhz to obtain precise 0.1 hz resolution, the frequency of the refclk signal will then be either 10 or 5 mhz. it can be used in conjunction with a phase locked loop (pll) to lock the 80 mhz clock generator to a reference standard frequency at one of these two frequencies. ldclk the l oad cl oc k output signal is the clock input divided by two. this clock is used for loading the phase and frequency data from the buffer registers to the phase alu and d -phase register, respectively. this output can be used to determine the exact clock cycle during which these transfers will take place, as shown in the timing diagrams. the transfers will take place on the rising edge of the clk following the falling edge of frld or phld when ldclk is low. since the propagation delay of this output from the rising edges of the clock input is comparable to the clock period at 80 mhz, care should be taken when using this output to synchronize the phase and frequency changes. if this signal is not used, there is a 50% probability that the phase and frequency changes will occur one cycle of the clock input later than specified. wrstb the wr ite st ro b e input is used to latch the data on the data 34-0 and phase 2-0 busses into the device. on the rising edge of the wrstb input, the information on the busses is transferred to the buffer register selected by the addr 2-0 bus. frld the fr equency l oa d input is used to control the transfer of the data from the d -phase buffer registers to the d -phase register. the data at the output of the buffer registers must be valid from the falling edge of frld until after the next rising edge of ldclk . the data is then transferred during the subsequent cycle. the frequency of the nco output will change 37 clock cycles after the frld command due to pipelining delays if ldclk was low at the time; otherwise it will change 38 clock cycles later. the maximum frequency update rate of the device is once every 9 clock cycles. phld the ph ase l oa d input is used to control the transfer of the data from the phase buffer registers to the phase alu. the data at the output of the buffer register must be valid from the falling edge of phld until after the next rising edge of ldclk . the data is then transferred during the subsequent cycle. the phase of the nco output will change 17 clock cycles after the phld command due to pipelining delays if ldclk was low at the time; otherwise it will change 18 clock cycles later. cin the c arry in put is an arithmetic carry to the least significant bit of the accumulator. normal operation of the nco requires that cin be set at a logic 0. when cin is set at a logic 1 the effective value of the d -phase register is increased by one. this allows the resolution of the accumulator to be expanded for higher frequency resolution. clksel the cl oc k sel ect input selects the frequency of the refclk output. when clksel is set low the frequency of refclk will be the clock frequency divided by eight, and when it is set high the frequency will be the clock frequency divided by sixteen.
7 stel-1176 electrical characteristics absolute maximum ratings warning : stresses greater than those shown below may cause permanent damage to the device. exposure of the device to these conditions for extended periods may also affect device reliability. all voltages are referenced to v ss . symbol parameter range units t stg storage temperature C40 to +125 c (plastic package) ? C65 to +150 c (ceramic package) v ddmax supply voltage on v dd C0.3 to + 7 volts v i(max) input voltage C0.3 to v dd + 0.3 volts i i dc input current 10 ma recommended operating conditions symbol parameter range units v dd supply voltage +5 5% volts (commercial) ? +5 10% volts (military) t a operating temperature (ambient) 0 to +50 c (commercial) (70 case) ? C55 to +125 c (military) d.c. characteristics (operating conditions: v dd = 5.0 v 5%, vss = 0 v, t a = 0 to 50 c, commercial v dd = 5.0 v 10%, vss = 0 v, ta = C55 to 125 c, military) symbol parameter min. typ. max. units conditions i dd(q) supply current, quiescent 1.0 ma static, no clock i dd supply current, operational 3.0 ma/mhz v ih(min) high level input voltage standard operating conditions 2.0 volts logic '1' extended operating conditions 2.25 volts logic '1' v il(max) low level input voltage 0.8 volts logic '0' i ih(min) high level input current 10 35 110 m a cin and csel , v in = v dd i ih(min) high level input current 10 m a all other inputs, v in = v dd i il(max) low level input current C10 m a cin and csel , v in = v ss i il(max) low level input current C15 C45 C130 m a all other inputs, v in = v ss v oh(min) high level output voltage 2.4 4.5 volts i o = C4.0 ma v ol(max) low level output voltage 0.2 0.4 volts i o = +4.0 ma i os output short circuit current 20 65 130 ma v out = v dd , v dd = max C10 C45 C130 ma v out = v ss , v dd = max c in input capacitance 2 pf all inputs c out output capacitance 4 pf all outputs
stel-1176 8 nco reset sequence nco frequency change sequence data 7-0 out 11-0 frld clock wrstb csel addr 2-0 don't care don't care don't care 37 clock edges old frequency new frequency don't care t su t hd t wr t cl t su t w t co don't care t ch t cc ldclk reset clock ldclk 11 10 78 11 clock edges t rs 9 refclk out 11-0 801 h not valid 123456 clksel = 1 ( ? 8) clksel = 0 ( ? 16) t sr
9 stel-1176 nco phase change sequence data 7-0 out 11-0 phld clock wrstb csel addr 2-0 don't care don't care 17 clock edges old phase new phase don't care t su t hd t cl t su t w t co t ch t cc ldclk don't care
stel-1176 10 applications information: locking the 80 mhz clock generator for the stel-1176 to a 10 mhz reference electrical characteristics a.c. characteristics (operating conditions: v dd = 5.0 v 5%, v ss =0 v, t a = 0 to 50 c, commerical v dd = 5.0 v 10%, v ss =0 v, t a =C55 to 125 c, military) commercial military symbol parameter min. typ. max. min. typ. max. units conditions t rs reset pulse width 20 25 nsec. t sr reset to clock setup 8 12 nsec. t su data , addr or csel 6 8 nsec. to wrstb setup, and frld or phld to clock setup t hd data , addr or csel 3 5 nsec. to wrstb hold, and frld or phld to clock hold t ch clock high 5 nsec. f clk = 80 mhz t cl clock low 5 nsec. f clk = 80 mhz t ch clock high 8 nsec. f clk = 60 mhz t cl clock low 8 nsec. f clk = 60 mhz t w wrstb , frld or phld 5 8 nsec. pulse width t co clock to output delay 7 14 3 20 nsec. load = 15 pf t cc clock to ldclk delay 7 20 3 28 nsec. load = 15 pf t cr clock to refclk delay 7 17 3 25 nsec. load = 15 pf dac clk 12 stel-1176 nco 35 mhz lpf 80 mhz oscillator bcd freq. control 0-35 mhz out 10mhz ref. 35 pll refclk
11 stel-1176 the sine signals generated by the stel-1176 have 12 bits of amplitude resolution and 15 bcd bits of phase resolution which results in spurious levels which are theoretically at least 72 db down. the highest output frequency the nco can generate is half the clock frequency (f c /2), and the spurious components at frequencies greater than f c /2 can be removed by filtering. as the output frequency f o of the nco spectral purity in many applications the nco is used with a digital to analog converter (dac) to generate an analog waveform which approximates an ideal sinewave. the spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the dac. applications information: data bus connections for data loading in the byte-wide mode d0 d1 d2 d3 d4 d5 d6 d7 stel-1176 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34
stel-1176 12 approaches f c /2, the "image" spur at f c C f o (created by the sampling process) also approaches f c /2 from above. if the programmed output frequency is very close to f c /2 it will be virtually impossible to remove this image spur by filtering. for this reason, the maximum practical output frequency of the nco should be limited to about 40% of the clock frequency. a spectral plot of the nco output after conversion with a dac (sony cx20202a-1) is shown below. in this case, the clock frequency is 80 mhz and the output frequency is programmed to 12.3456789 mhz. this 10-bit dac gives better performance than any of the currently available 12-bit dacs at clock frequencies higher than 10 or 20 mhz. the maximum non- harmonic spur level observed over the output frequency range shown in this case is C59 dbc. the spur levels are limited by the dynamic linearity of the dac. it is important to remember that when the output frequency exceeds 25% of the clock frequency, the second harmonic frequency will be higher than the nyquist frequency, 50% of the clock frequency. when this happens, the image of the harmonic at the frequency f c C 2f o , which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through f c /3. it would be necessary to select a dac with better dynamic linearity to improve the harmonic spur levels. (the dynamic linearity of a dac is a function of both its static linearity and its dynamic characteristics, such as settling time and slew rates.) at higher output frequencies the waveform produced by the dac will have large output changes from sample to sample. for this reason, the settling time of the dac should be short in comparison to the clock period. as a general rule, the dac used should have the lowest possible glitch energy as well as the shortest possible settling time. typical spectrum center frequency: 15.0 mhz frequency span: 30.0 mhz reference level: C10 dbm resolution bandwidth: 1 khz scale: log, 10 db/div output frequency: 12.3456789 mhz clock frequency: 80 mhz

!

"

#

!

!

!

$

!

!"
#$%
&'"()"* + $#%#
$%
&'"()"* + ,-&'"()"* (((

▲Up To Search▲

Price & Availability of STEL-1176MC

	To Download STEL-1176MC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .